Xilinx ISE Design Suite WebPack Edition

The WebPack Edition is the free (and of course limited) Software to design Xilinx CPLDs and smaller FPGAs. Upgrade to more powerful version is available for a fee. For latest FPGAs use Vivado instead.

Installation for Linux

Create Startup Wrapper (for amd64 architecture)

#!/bin/sh
# Starts Xilinx ISE SW in a terminal
# Needs to source settings beforehand
# Command line argument "blank" does not invokes ise, just leaves the blank terminal with the settings loaded

# Argument parser
case "$1" in
  "blank" | "noise")
    # Just start a shell
    INVOKE_TOOL="bash"
    ;;
   "")
    # Invoke ise
    INVOKE_TOOL="ise"
    ;;
   *)
    echo "Unknown Argument $1"
    exit 1
    ;;
esac

# Required for running floorplan editor
DISPLAY=:0
export DISPLAY
echo "Setting DISPLAY to $DISPLAY to satisfy floorplan tool"

# Xterm is smaller font, replace with your favourite terminal
echo "${INVOKE_TOOL}"
xterm -e bash -c "cd /opt/xilinx_ise/14.5/ISE_DS/; . ./settings64.sh; ${INVOKE_TOOL}"

Errors and Workarounds

Change Brower settings to open web pages from within ISE
  • Option below Edit/Preferences
  • Fixes errors like:
    XPCOMGlueLoad error for file /usr/lib/xulrunner-10.0/libxpcom.so: libxul.so: cannot open shared object file: No such file or directory
    Couldn't load XPCOM.
  • Use same helper script as for Quartus II Software

Error for launching Floorplanning
  • /home/opt/xilinx_ise/14.5/ISE_DS/ISE/bin/lin64/_pace_old: error while loading shared libraries: libXm.so.3: cannot open shared object file: No such file or directory
    • Fix:
      sudo aptitude install libmotif4
      cd /usr/lib; sudo ln -s libXm.so.4 libXm.so.3
  • /home/opt/xilinx_ise/14.5/ISE_DS/ISE/bin/lin64/_pace_old: error while loading shared libraries: libstdc++.so.5: cannot open shared object file: No such file or directory
    • Fix:
      sudo aptitude install libstdc++5
  • Wind/U X-toolkit Error: wuDisplay: Can't open display
    • Fix:
      DISPLAY:0; export DISPLAY=
    • Already incorporated in startup script above

Fuse compilation of simulation executabe fails with compile error messages in Debian Wheezy

The message is

FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files.
   
      Please recompile with -mt off -v 1 switch to identify which design unit failed.  For technical support on this issue, please visit http://www.xilinx.com/support.
   FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files.
   
      Please recompile with -mt off -v 1 switch to identify which design unit failed.  For technical support on this issue, please visit http://www.xilinx.com/support.

Messages when adding -mt off -v 1 to the compile commands

   /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1: /home/opt/xilinx_ise/14.5/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/x86_64-linux-gnu/libppl_c.so.4)
   /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1: /home/opt/xilinx_ise/14.5/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/x86_64-linux-gnu/libppl_c.so.4)
   /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1: /home/opt/xilinx_ise/14.5/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/x86_64-linux-gnu/libppl_c.so.4)
   /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1: /home/opt/xilinx_ise/14.5/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/x86_64-linux-gnu/libppl.so.12)
   /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1: /home/opt/xilinx_ise/14.5/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/x86_64-linux-gnu/libppl.so.12)
   /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1: /home/opt/xilinx_ise/14.5/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/x86_64-linux-gnu/libppl.so.12)
   FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/Testbench_isim_beh.exe.sim/work/p_0013066497.c
   
        For technical support on this issue, please visit http://www.xilinx.com/support.
   FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/Testbench_isim_beh.exe.sim/work/p_0013066497.c
   
        For technical support on this issue, please visit http://www.xilinx.com/support.

Confirm error with (after loading the ISE settings): ldd /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1

Fix, as suggested in https://bbs.archlinux.org/viewtopic.php?id=111551

cd /home/opt/xilinx_ise/14.5/ISE_DS/ISE/lib/lin64
  sudo mv libstdc++.so libstdc++.so-org
  sudo mv libstdc++.so.6 libstdc++.so.6-org
  sudo mv libstdc++.so.6.0.8 libstdc++.so.6.0.8-org
cd /home/opt/xilinx_ise/14.5/ISE_DS/common/lib/lin64/
  sudo mv libstdc++.so libstdc++.so-org
  sudo mv libstdc++.so.6 libstdc++.so.6-org
  sudo mv libstdc++.so.6.0.8 libstdc++.so.6.0.8-org

Then the system libraries are used: ldd /usr/lib/gcc/x86_64-linux-gnu/4.7/cc1 - No error anymore

Don't forget: Before starting compilation again you need to manually delete the isim/ directory and run Project/Cleanup Project Files

Documentation

ISE Design Suite SW Manual (Online)
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/isehelp_start.htm
ISE In-Depth Tutorial (Older Version)
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ise_tutorial_ug695.pdf
ISim In-Depth Tutorial
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/ug682.pdf
ISim User Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/plugin_ism.pdf

Synthesis and Simulation Design Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/sim.pdf
XST User Guide for Virtex-4/5, Spartan-3, CPLD, Including HDL Coding Techniques and VHDL/Verilog Language Support
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/xst.pdf
CPLD Libraries Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/cpld_all_scm.pdf
Timing Closure User Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/ug612.pdf
Constraints Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/cgd.pdf
Command Line Tools User Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/devref.pdf

Language Support

  • Language Support very old, and even further constructs are not supported
  • VHDL IEEE-STD-1076-1993 and 200x (some constructs)
  • Verilog IEEE-STD-1364-2001
  • Standard Delay Format (SDF) version 2.1

General Usage Hints

  • Edit/Language Templates for Tcl/HDL Code Templates and Device Macros
    • Source code/Component declarations: /opt/xilinx_ise/14.5/ISE_DS/ISE/vhdl/src/unisims/
    • If you include the library UNISIM no component declation is needed
  • Assign Device Pins
    • Design Browser Sidebar/Implementation/User Constraints/Floorplan IO
  • Delete simulation executables and temporary files
    • When deleting by hand will get "WARNING: ProjectMgmt - File ... is missing"
    • Use: Project/Cleanup Project Files instead

Simulation

General

  • Apply stimulus data after 100 ns in order to account for the default Global Set/Reset (GSR) pulse used in SIMPRIM-based simulation
  • Post Fit netlist uses always std_logic(_vector), even when hdl is written with std_ulogic(_vector)
    • Problem: You cannot bind std_ulogic_vector with std_logic_vector (std_logic and std_ulogic works)
    • Workaround: Always use std_logic_vector at toplevel (std_ulogic is fine)

Run with VHDL configurations

  • Project/Manual compile order
    • Only select for Simulation, not Implementation
  • Specify Toplevel module as wanted configuration for rtl and post-fit
  • Behavioral Check Syntax not working anymore - tries to also check the post configuration
    • Compilation respects the selection of enabled/disabled modules
    • Maybe could be fixed with Custom Project File in Processs Properties

Gatelevel Simulation

  • Post Simulation (with Timing) is recommended
  • Enable Post-Fit Simulation model creation in
    Design Sidebar/Implement Design/Process Properties/Simulation Model
  • Create Post-Fit Simulation Model, below
    Design Browser Sidebar/Implementation/Implement/Design/Optional Implementation Tools
  • Switch to Simulation/Post-Fit
    • Configure properties with right-click Simulate Post-Fit Model/Process Properties
    • Run it

Timing Analysis (STA), Timing Constraints and Closure

General

  • (Timing) Constraints GUI started with Tools/Constraints Editor
  • Need to generate report with
    Implementation Side Pane/Implement Design/Optional Implementation .../Generate Timing
  • The analysis of asynchronous reset paths, including the recovery time and reset pin to output time, is not included in the Period constraint analysis by default.
    • In order to see asynchronous reset and asynchronous set paths, enable a path tracing control (PTC) as follows
      ENABLE = REG_SR_R;
    • For recovery time
      ENABLE = REG_SR_O;

Known Issues

  • Do not use decimal points in timing - these constraints are silently dropped
  • So instead of writing "0.5 MHz" you have to write "2000 ns"
  • Advice: Do not use Hz, use always ns as unit instead

CPLD Specific

  • When using CLK_DIVx macro (clock divider in CoolRunner-II CPLD) then you need to apply the original timing to the Clock divider output
  • Timing analysis will itself divide the timing constraint down
  • Example: 8 MHz clock, CLK_DIV16 macro used (output net is clk_div_by16):
    NET "clk_div_by16" TNM_NET = clk_div_by16;
    TIMESPEC TS_clk_div_by16 = PERIOD "clk_div_by16" 8 MHz HIGH 50%;
  • See full comment in Xilinx Forum
  • For CPLD designs, clock inputs referenced by Offset constraints must be explicitly assigned to a global clock pin using either a BUFG symbol or applying the BUFG=CLK constraint to an ordinary input.

Device Programming

For Coolrunner II Starter Board (and supposely any other board from Digilent) you can use the Digilent Adept Software


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Topic revision: r2 - 2013-06-01 - 18:56:22 - RoLaUser

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